Download Analogue-digital ASICs : circuit techniques, design tools by R.S. Soin, F. Maloberti, J. Franca PDF

By R.S. Soin, F. Maloberti, J. Franca

A wide-ranging booklet near to combined analogue electronic ASICs, this name covers processing
technology, circuit options and construction blocks, layout and functions, and CAD and helping instruments

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Extra resources for Analogue-digital ASICs : circuit techniques, design tools and applications

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The implant and subsequent drive conditions for the shunt region have been carefully chosen to provide the optimum electrical characteristics for the BJT. This was done using a combination of careful measurement, statistical experimental design and process modelling. 4 Island defination and field implants After shunt processing, the field regions receive a boron implant (not shown) to prevent leakage across these regions due to the turning on of parasitic MOSFETs. This implant is termed 'n-field', the mask being generated from the n-well mask, in a similar manner to the p-well mask.

7b shows the emitter cut through the thin oxide and the poly-silicon implant (emitter implant). 8) The next main processing step is the definition of the poly-silicon layer, which defines the gate size and the emitter contact. Following the gate etch, 21 Technology and Modeling Issues for an advanced BiCMOS ASIC process the contact implants are performed - phosphorus implants for the N + contacts to NMOS (n-channel MOS) sources/drains and BJT collectors and a boron implant for the P+ contacts to PMOS (p-channel MOS) sources/drains and BJT bases.

This has the advantage that the model can be directly related to real effects. The main disadvantage is that the model can become cumbersome and is no longer 'compact'. Other models are based on curve-fitting to the device characteristics. These models tend to be fast, but can suffer when device geometries reduce and other physical effects become dominant, which cannot be accounted for in the curve fitting algorithms. Another distinction between models is whether they are designed for scaling. Some models try to predict the performance of transistors of all sizes with one set of input parameters, whereas others require a different set of parameters for each device size.

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